Mainstream Development Flows
FirstPass provides ASIC and FPGA design services to industry leading Fortune 100 technical companies. These customers expect nothing less than leading edge state of the art tools, processes and design flows. We believe that remaining synchronized to mainstream development flows maximizes the re-use potential of product development, and helps reduce the risk that can accompany the use of one-off or obscure flows and tools.
Design and Verification Re-use
FirstPass is experienced with many different verification methodologies including traditional Verilog and VHDL testbenches, and advanced verification environments developed around higher level languages such as Vera, Specman, SystemVerilog VMM, OVM and UVM. FirstPass’s preferred verification methodology is UVM, which is considered the “industry-ideal” solution that effectively combines performance and reusability. UVM is designed to boost productivity in the development of your current verification environment, and what is created now can easily be leveraged as productivity gains on many generations of follow-on projects.
UVM is a SystemVerilog class library developed and maintained by Accellera, with an Open Source reference implementation. These base classes provide the testbench structure, simulation execution phases, communication channels among agents, reporting methods, error tracking and pass-fail indications, timeout timers, etc., which all testbenches need in one form or another. Less time “reinventing the wheel” equals more time for your important and value-added verification project. The top-level testbench environment can be built quickly using the built-in capabilities of UVM, and the intelligent agents that do the real work of verification can be quickly integrated.
Follow-on projects can reuse code from the previous project, even when changes are required. Using SystemVerilog object-oriented programming techniques and the UVM “factory” structure, any agent or even complete testbench environments can be easily extended and reused. New functionality can be added, old functionality can even be replaced entirely, without having to rebuild everything from scratch or maintain multiple copies of nearly-identical source code.
Two testbench environments built with UVM have a similar “look-and-feel”. This makes for a shorter learning curve for a new engineer joining the project, reducing their time to productive work. When a new verification project starts, having a “template” to copy from is very useful. The previous UVM testbench environment is an excellent basis for creating the new project, and can also be a great training tool for engineers new to UVM.
Bounded Verification Strategies
FirstPass believes in establishing a managed, disciplined approach to the verification process using objective criteria to clearly convey pass/fail, which in turn helps quantify risk at the completion of the development process.
- Rigor and discipline in verification, turns the “art” of verification into a “science”
- Based on our experience with time-proven project management techniques and quality assurance processes (military, aerospace, DO-254, etc.)
- Design specification is key, it is the source of all verification activity
- Verification requirements are derived from the design spec, these provide a detailed description of the input conditions to the DUT and expected results from the DUT, specific coverage items are defined to measure and report the correct functionality of each requirement
- Verification test plan documentation is created to partition and specify the verification code development, using the design spec and verification requirements
- The list of detailed verification requirements serves several important purposes:
- Verification requirements get prioritized, ensuring that critical design features are verified first and best, and helps manage schedule if a design feature is not available until later
- Development status of the verification coverage items is tracked and reported
- Coverage results from simulation are referenced back to the individual verification requirement and reported
- Coverage results of all the requirements is gathered from regression simulation and reported, which helps determine when verification is complete, and to assess risk of any unverified requirements when the design is released
Using the QuickRamp method to develop a verification environment assures that the final product is in alignment with industry standard methods and techniques for the creation of a SystemVerilog test environment. You can be assured of the ability to integrate with other test environment components and simulation tools from across the industry, both now and in the future.
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