Careers

FirstPass Engineering has been providing digital and analog solutions for their customers since 1993. Whether it be designing in the latest ASIC/FPGA technology or utilizing the most advanced verification methods to assure that a customer’s product is RIGHT THE FIRST TIME, you will find FirstPass Engineering to be an exciting work environment that offers an exceptionally high level of exposure to a wide variety of products with many leading-edge commercial, military, and aerospace companies.

We are looking for design and verification engineers in the Castle Rock and Phoenix offices with varying levels of experience that relish the opportunity to utilize, broaden, and grow their skills and enjoy the continued success and growth that FirstPass Engineering has experienced for over 20 years. Providing highly specialized solutions across large market segments for an endless variety of products is challenging and rewarding, and offers significant opportunity for personal growth as well as leadership opportunities.

Careers

We are always seeking highly qualified Design and Verification Engineers. We offer competitive compensation packages, outstanding benefits, and a high quality-of-life work environment.

For consideration, please send your resume to careers@firstpasseng.com.


Current Job Openings

Senior ASIC Verification Engineer

The ideal candidate will have a Bachelor’s Degree in Electrical Engineering, Computer Engineering, or Computer Science with five to ten years of experience in the verification of ASIC/FPGA devices.

The following skills and experience are required:

  • Strong understanding of verification process and flow
    • Join a project at any phase with minimal disruption
    • Participate as a lead and/or contributor
    • Quickly adapt to a variety of different environments, methods and standards
  • Ability to create a high-level verification plan
    • Derivation of verification requirements from design requirements
    • Derivation of project schedule from verification requirements
    • Architecting a complex test environment
    • Identification and integration of re-use
  • Ability to create a complex constrained random test environment
    • Setup, build and run test benches
    • Develop agents for complex interfaces (protocol/retries/split transactions)
    • Application of direct and random methods
    • Application of coverage analysis (types and convergence methods)
    • Analyzing and debugging failures to establish root cause
    • Application of assertions
  • Strong understanding of Object Oriented Programming (classes, methods, polymorphism)
  • Use of a high-level language for verification, such as SystemVerilog C++, Java, etc.
  • Experience with verification methodologies (OVM/UVM)
  • Highly skilled with one or more industry standard simulation tools such as Mentor Questa-ModelSim, Synopsys VCS, or Cadence NCSIM
  • Strong understanding of typical design structures (FIFO’s, pipelines, memories, state machines, etc.)
  • Strong understanding of standard protocols (PCI Express, Ethernet, etc.)
  • Comfortable and confident interacting with customers
  • Excellent written and verbal communication skills

The following additional skills and experiences would be a plus:

  • Experience verifying hierarchically partitioned large ASICs
  • SystemVerilog/C++ co-simulation
  • Overall knowledge of the ASIC development process
  • RTL design experience
  • Ability to train/mentor junior engineers

Must be a US Person as defined in EAR 15 CFR Part 772 and ITAR 22 CFR Section 120.15, which includes US Citizenship, US Permanent Residence, or a Protected Person under 8 U.S.C. 1324b(a)(3).

Principal CPU Architecture/Design Engineer

The ideal candidate will have a Bachelor’s Degree in Electrical or Computer Engineering with at least ten years of experience in CPU or similar complexity ASIC microarchitecture and design

The following skills and experience are required:

  • Experience with CPU or similar complexity ASIC development
    • Harvard and RISC architectures
    • Design partitioning and micro-architecture definition
    • Detailed documentation of interfaces, data flow, logic structures, pipelines, etc.
    • High performance physically aware RTL coding
    • Fundamental verification skills and interaction with a verification team
  • Solid understanding of commonly used CPU structures
    • Transposing ISA descriptions into fundamental processing elements such as instruction decoding, queuing, buffering, predication and branch prediction, etc.
    • Multi-level instruction/data cache design
    • FP ALUs, GP Regs, Accumulators
    • Multi-thread pipelining, synchronization and exception handing
    • Integration of high bandwidth memory and IO interfaces
  • Solid working experience with industry standard CAD tools and ASIC development flows
  • Scripting, e.g. with Perl, Tcl, Python, etc…
  • Excellent written and verbal communication skills
  • Comfortable and confident interacting with customers
  • Ability to support occasional travel

The following additional skills and experiences would be a plus:

  • RTL design for multi-threaded, low-power, out-of-order processor design
  • Demonstrated success in RTL design of CPU/DSP logic blocks
  • Recursive architectural evolution and performance tuning using hardware/software modeling methods
  • Project leadership, including task definition, planning and estimating
  • Deep-submicron ASIC technologies and flows
  • Experience with aspects of DFT, JTAG and boundary scan
  • Master’s Degree in Electrical or Computer Engineering

Must be a US Person as defined in EAR 15 CFR Part 772 and ITAR 22 CFR Section 120.15, which includes US Citizenship, US Permanent Residence, or a Protected Person under 8 U.S.C. 1324b(a)(3).

Senior ASIC Design Engineer

The ideal candidate will have a Bachelor’s Degree in Electrical or Computer Engineering with five to ten years of experience in the design of ASIC/IC devices.

The following skills and experience are required:

  • Previous development of a large ASIC or a component within an ASIC
    • Capture and documentation of design requirements
    • Design partitioning and micro-architecture
    • RTL coding (Verilog or VHDL)
    • Setup and execution of synthesis and timing closure flows
    • Fundamental verification skills and interaction with a verification team
  • Solid understanding of standard design methods
    • Synchronous design practices
    • Clocking (domain crossing and skew management)
    • Data flow management (FIFOs, memories, pipelining)
  • Solid understanding of I/O planning and buffer selection
  • Solid working experience with industry standard CAD tools and ASIC development flows
  • Comfortable and confident interacting with customers
  • Ability to support occasional travel
  • Excellent written and verbal communication skills

The following additional skills and experiences would be a plus:

  • Deep-submicron ASIC technologies and flows
  • Experience with aspects of DFT, JTAG and boundary scan
  • Use of a high-level language for verification, such as SystemVerilog C++, Java, etc.
  • Mixed signal design experience and the tools associated with it
  • Experience with ASIC P&R tools such as ICC or Silicon Encounter
  • Experience as a Project or Team Lead
  • Master’s Degree in Electrical or Computer Engineering

Must be a US Person as defined in EAR 15 CFR Part 772 and ITAR 22 CFR Section 120.15, which includes US Citizenship, US Permanent Residence, or a Protected Person under 8 U.S.C. 1324b(a)(3).

SW Application Development Engineer

Objective is to develop C++ software that can provide early exposure to architectural-based performance issues for highly scalable array of fully custom CPUs. Candidate will help develop suite of algorithms and simple usage models that are representative of end-client applications. The multi-processor system is architected for a very specific purpose and incorporates a new ISA. Applications need to be specifically structured to exacerbate and stress the highly distributed and networked nature of the multi-processor system.

The following skills and experience are required:

  • Experience architecting and developing performance-based application software for a highly scalable CPU design
  • Direct experience working with C behavioral models to verify microprocessor designs
  • Knowledge and experience of computer architecture, multiprocessing, and fundamentals including RISC microarchitecture and pipeline design concepts
  • Strong software design skills in C, C++, Python, and Linux

The following additional skills and experiences would be a plus:

  • Experience in applications development for supercomputer usage
  • Knowledge of mathematical and software algorithms is a plus (FFT, Matrix Multiply, Sort)
  • Effective at identifying performance-driven issues and using modeling to assist with convergence on architectural trade-offs

Must be a US Person as defined in EAR 15 CFR Part 772 and ITAR 22 CFR Section 120.15, which includes US Citizenship, US Permanent Residence, or a Protected Person under 8 U.S.C. 1324b(a)(3).