Secure from Concept to Production

ASIC & FPGA

Design

FirstPass is a full-service, one stop shop that can execute all, or any portion, of the product development process, from concept to production.

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Define

Requirements, Partitioning and Architectural Definition

 

We understand the relationship between specification and implementation, and know how to partition designs and make trade-offs necessary for performance, risk mitigation, and functional flexibility.

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Digital Design

Our expertise includes digital, mixed signal, analog, I/O, memories, and very high speed circuitry including SerDes. We also have RTL expertise in both VHDL and Verilog. We have taken hundreds of designs from specification through to fabrication. We have directly related experience that meets your requirements and type of project.

Digital Design

  • VHDL, SystemVerilog
  • RTL, C to RTL
  • Design IP integration
  • DesignWare, process libraries (memory, I/O, SERDES, etc.)
  • 3rd-party design IP
  • Multiple voltage and power domains
  • SOC integration and HW/SW co-design
  • Design-for-synthesis
  • Synopsys Design Compiler, FPGA vendor specific tools
  • Design-for-test
  • Design-for-verification/debug

Analog/Mixed Signal

  • I/O design
  • SerDes, DDR3, Analog
  • PLL, DLL design
  • Band gap reference generator
  • Standard cell libraries
  • SRAM, DRAM
  • Sense amps, current amplifiers
  • Various timing circuits
  • SerDes PHY design and layout

Macros & Protocols

  • CSIX
  • PCIe Gen1/2/3
  • PCI
  • SPI 4.2
  • Infiniband
  • Rapid IO, Serial RIO
  • ARM Core
  • HyperTransport3
  • CPRI
  • SONET
  • SAS (Serial Attach SCSI)
  • SATA
  • Fibre Channel
  • Ethernet
  • 2-Wire Serial
  • USB
  • XAUI
  • JESD204A/B
    …and many more
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Synthesis & Timing Closure

Synthesis and timing closure starts with robust design. We understand how to architect and code to meet timing and optimize power and area. Good synthesis planning pays dividends in physical implementation. We have experience with many synthesis and static timing analysis tools such as Design Compiler, PrimeTime, Synplify, Altera Quartus, Xilinx XST, and Magma.

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Functional Verification

Process

  • Verification Plan to specify DV approach and function
  • Verification Requirements Matrix to define and track Verification Requirements, coverage methods, priorities
  • Automated reporting of actual coverage results versus Verification Requirements
  • Reviews to monitor and track coverage closure

Methodology

  • Constrained-random generation of stimulus
  • Coverage-driven Verification
  • Stand-alone intelligent agents, checkers, scoreboards
  • Assertions in RTL and Verification code

Implementation

  • SystemVerilog and UVM/OVM/AVM/VMM
  • Fewer test cases, more randomization of setup/traffic
  • Verification IP integration
  • Automated reporting of actual coverage results versus verification requirements
  • Directed testing where necessary or more efficient
  • Verilog, VHDL, e, C/C++/SystemC models and testbenches

Platforms

    • Mentor ModelSim, Questa
    • Cadence Incisive
    • Synopsys VCS
    • Aldec Riviera-PRO
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Physical Design

Full Custom Layout

  • Device matching
  • Parasitic extraction
  • LOD effects
  • Well proximity effects

Place & Route

  • Full chip floorplanning
  • Hierarchical and flat design
  • IP integration
  • Physical constraint generation
  • STA and timing closure
  • Power bussing and power analysis
  • Signal integrity
  • Physical verification (LVS, DRC, ERC)

LEF & .LIB Generation